Semiconductor devices are used in a large number of electronic devices such as computers, cell phones and others. One of the goals of the semiconductor industry is to continue shrinking the size and increasing the speed of individual devices. Smaller devices can operate at higher speeds since the physical distance between components is smaller. In addition, higher conductivity materials such as copper are replacing lower conductivity materials such as aluminum. One other challenge is to increase the mobility of semiconductor carriers such as electrons and holes.
One technique to improve transistor performance is to mechanically strain (i.e., distort) the semiconductor crystal lattice near the charge-carrier channel region. Transistors built on strained silicon, for example, have greater charge-carrier mobility than those fabricated using conventional substrates. One way to create strain is to provide a stress layer over the transistor. Variants of stress layers can be used for mobility and performance boost of devices. For example, stress can be provided by a contact etch stop layer (CESL), single layers, dual layers, stress memory transfer layers, and STI liners. Most of these techniques use nitride layers to provide tensile or compressive stresses; however, other materials can be used in other applications, e.g., HDP oxide layers.
Another technique to strain silicon is to provide a layer of germanium or silicon germanium. A thin layer of silicon may be grown over the germanium-containing layer. Since the germanium crystal lattice constant is larger than the silicon lattice constant, the germanium-containing layer creates a lattice mismatch stress in adjacent layers. Due to the different lattice structures, the SiGe will impart a strain onto the silicon layer. This strained silicon layer can be utilized to fabricate faster transistors.
One example of making a strained-silicon CMOS device with a shallow trench isolation (STI) oxide region is disclosed in U.S. Patent Application Publication No. 2005/0101077, which is incorporated herein by reference. In this method, a silicon substrate is formed and a relaxed-SiGe layer is formed over the silicon substrate or a SiGe-on-insulator substrate with a buried oxide (BOX) layer. A strained-Si layer overlies the relaxed-SiGe layer. A silicon oxide layer is formed over the strained-Si layer and a silicon nitride hardmask layer is formed over the silicon oxide layer. The silicon nitride layer, the silicon oxide layer, the strained-Si layer, and the relaxed-SiGe layer are etched to form an STI trench. A sacrificial oxide liner is formed on the STI trench surface to round and reduce stress at the STI trench corners. The sacrificial oxide liner is then removed and the STI trench is filled with silicon oxide.
As another example, U.S. Patent Application Publication No. 2004/0173815, which is incorporated herein by reference, discloses a method of fabricating a strained-channel transistor structure. A substrate includes a first semiconductor material with a first natural lattice constant, a gate dielectric layer on the substrate, a gate electrode on the gate dielectric layer, a source region and drain region oppositely adjacent to the gate dielectric layer, and a spacer on a sidewall of the gate electrode. One or both of the source region and drain region are recessed to form a recess. The recess can then be filled with a second semiconductor material with a second natural lattice constant different from the first natural lattice constant as a lattice-mismatched zone.